The present disclosure relates to a semiconductor memory device, and more particularly to a strobe signal controlling circuit.
Generally, a semiconductor memory device employs a strobe signal DQS by using a short pulse signal used to synchronize with an external chip set in order to transmit data during the transmission or the reception of data.
FIG. 1 is a block diagram showing a conventional strobe signal controlling circuit.
As shown in FIG. 1, according to the conventional strobe signal controlling circuit, an initial write controller generates a signal WT0 after receiving a pulse signal WTP generated by decoding a write command and synchronizing the pulse signal WTP to a clock signal CLK, so that signals WT1 to WT8 are generated through a DQS signal outputting unit. The signals may be selected according to burst lengths. The signals are selected according to the burst lengths BL in a DQS selection unit so that a signal DQS_OFF_CTRL is output. A reset signal generator outputs a reset signal to reset the output of each shift register provided in the DQS signal outputting unit.
FIG. 2 is a circuit diagram of the initial write controller shown in FIG. 1. If the signal WTP is applied to the initial write controller, the signal WT0 is enabled and then not disabled until a next high-level clock pulse is applied.
FIG. 3 is a circuit diagram of the reset signal generator shown in FIG. 1. When receiving the signal WTP, that is, receiving a new write command, the reset signal generator resets the DQS signal outputting unit. In addition, even when receiving a signal RST, which is generated upon MRS or power-up, the reset signal generator performs a reset operation. In a read operation, the reset signal generator performs the reset operation.
FIGS. 4 and 5 are operational timing charts of the strobe signal controlling circuit shown in FIG. 1. FIG. 4 illustrates the operation of the strobe signal controlling circuit in an ideal case, in which a write command corresponding to “BL=8” is consecutively applied twice. When the write command is input at a t1 clock pulse, the signal WTP is generated, and the signal WTP is inverted to generate a signal RSTB. The initial write controller generates the signal WT0 corresponding to one period of the clock signal. In addition, signals WT1 to WT4, which are sequentially shifted from the signal WT0 by one clock, are generated. Finally, the signal DQS_OFF_CTRL is generated. In this case, although the signal WT4 must be generated at a t5 clock pulse, the signal WT4 is not generated because the DQS signal generator is reset by the signal RSTB. Similarly, even in the second write operation, the signal WT0 is shifted by one period of the clock signal such that the signals WT1 to WT4 are generated. In this case, since the next write command does not exist, the signal WT4 is normally generated. Thereafter, the signal DQS_OFF_CTRL signal is generated to control the following DQS signal.
FIG. 5 illustrates a case in which the signal WTP is applied prior to the signal CLK. The signal RSTB is generated in the same time point as that of the signal WTP. The signal WT0 is generated at the same time point as the enable time point of the signal WTP. In this case, when the signal WT0 is shifted to a shift register, the signal RSTB becomes a high level before the clock signal becomes a low level. In other words, since the clock signal is in the low level when the signal WT0 is shifted to the shift register, the signal WT0 is not shifted by ½ CLK, but signals prolonged by ½ CLK are generated. Accordingly, the signal WT1 is enabled from a time point, at which the low level of the signal RSTB is changed into the high level, to a next enable time point of the clock signal while maintaining a high level. Such signals are consecutively delivered through shift registers, and the signal WT4 exists in remaining duration except for a portion of a next write signal WTP, differently from that shown in FIG. 4. The signal WT4 becomes the signal DQS_OFF_CTRL as it is, to prevent the last falling DQS in the first write operation and a falling DQS in the second write operation from being generated, so that a write fail occurs.